DATA FOR HIGH-SPEED DATA TRANSFER BETWEEN LSI

摘要

PURPOSE: To operate with a clock frequency of higher speed by means or the same CMOS process. CONSTITUTION: In a system consisting of first and second LSIs 1 and 2 and a clock supply circuit 3 supplying a clock for these LSIs 1 and 2, signal transfer from first LSI 1 to second LSI 2 is executed by the synchronizing transfer of the latency of 1.5-clock and that from second LSI 2 to first LSI 1 is executed by the synchronizing transfer of the latency of 1.5 clock. In a system where the synchronizing transfer of the signal between LSIs 1 and 2 determines the upper limit of the frequency of a system clock, the upper limit of the frequency of the system clock can be improved to be 1.5-fold through the use of this method.