CLOCK SIGNAL DISTRIBUTION SYSTEM

摘要

PURPOSE: To fetch data without shifting even at the time of not executing the phase adjustment of a data signal and equalizing the length of a wire and to compensate for delay variation even when it is generated. CONSTITUTION: Respective packages 12 to 14 send clock signals back to a package 11. The package 11 is provided with PLL circuits 11b to 11d corresponding to the packages 12 to 14. The PLL circuits 11b to 11d phase-synchronize a clock signal Csa' to Csc' sent back from the corresponding packages 12 to 14 and a clock signal Cs generated by a clock generating source 11a. Outputs from these PLL circuits 11b to 11d are supplied to the corresponding packages 12 to 14 as clock signals Csa to Csc.