发明名称 ERASURE VERIFICATION CIRCUIT OF COLUMN- REDUNDANT NONVOLATILE SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To make it possible pass erasure verification even when there is an open bit line, improve the reliability of the erasure verification, and improve the yield of manufacture by changing fail data stored in a data latch, connected to an open normal bit line, into pass data. SOLUTION: For the erasure verification, a pass/fail detecting circuit 18 judges the erasure state of data of a memory cell array 10 stored in each data latch of a page buffer 16 and then outputs a fail signal to a column selecting circuit 20 when even one fail data is present. This fail data is selected by a column decoder 22 and the fail data stored in the data latch of the page buffer 16 connected to the open normal bit line is changed into pass data.
申请公布号 JPH08249896(A) 申请公布日期 1996.09.27
申请号 JP19960016501 申请日期 1996.02.01
申请人 SAMSUNG ELECTRON CO LTD 发明人 BOKU SHIYOUUKU;HAYASHI EIKO
分类号 G11C17/00;G11C16/02;G11C16/06;G11C29/00;G11C29/12 主分类号 G11C17/00
代理机构 代理人
主权项
地址