发明名称 |
Circuit de redondance de mémoire. |
摘要 |
The circuit includes a content addressable memory (CAM) storing addresses of faulty elements in a principal memory (MP). In use, incoming addresses (ADD) are compared with defective addresses stored in the content addressable memory (CAM) and where identical they are readdressed to a redundant memory (MR). Where the principal memory (MP) has no defects time may be saved by using an inhibiting circuit (IN). If the inhibiting circuit (IN) emits a validating signal (VAL) operation is normal but an inhibiting signal (INH) prevents comparison of addresses and all addresses proceed to the principal memory (MP). |
申请公布号 |
FR2716743(B1) |
申请公布日期 |
1996.09.27 |
申请号 |
FR19940002282 |
申请日期 |
1994.02.28 |
申请人 |
SGS THOMSON MICROELECTRONICS SA |
发明人 |
DEVIN JEAN |
分类号 |
G11C29/00;G11C29/04;G11C29/24;(IPC1-7):G11C29/00;G11C15/04 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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