| 摘要 |
a D-flipflop(F/F1) for receiving the horizontal sync. signal(V2) from a horizontal voltage control oscillator as a D-input and the clock pulse (V3) from the oscillator as a clock signal; an inverter(N1) for loading a flyback pulse to inverters(N2,N3) as an input signal; an inverter(N2) for changing its output according to Q_ of a D-flipflop output if the flyback pulse is low; transistors(Q7,Q10) for controlling transistors(Q8,Q9) of the differential amplifier which controls an output voltage(Verror); and a current mirror to get consistent outputs from the AFC circuit.
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