| 摘要 |
The device includes a clock output means for mixing horizontal synchronizing signal and vertical synchronizing signal and generating a clock signal, a delaying means(20) for delaying and generating the vertical synchronizing signal and a clock of clock output means during finite time, a recoding address output means(30) for generating an address signal continuously, a single address output means(40) for generating a single address signal, and selecting means(50) for generating the signal selectively.
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