| 摘要 |
A frequency synthesizer (200) which uses a direct digital synthesizer (DDS) (204) to generate a highly accurate periodic signal. The DDS (204) output signal is bandpass filtered utilizing a clean-up phase lock loop (PLL) (214) to produce a spectrally pure reference signal and promote overall fast settling time. A second or primary phase lock loop (220), having a much faster settling time than the first PLL (214), adjusts the frequency of the reference signal generated by the clean-up PLL (214). In one embodiment, the DDS frequency synthesizer (204) has a digital to analog converter (DAC) (206) coupled to the clean-up PLL (214). Another embodiment (300) feeds the most significant bit (MSB) (310) or overflow bit from the DAC accumulator (306) into the "clean-up" PLL (318). Yet another embodiment (400) uses a switching apparatus to bypass the "clean-up" PLL (410) while it is settling on a new frequency.
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