| 摘要 |
<p>A first signal ( phi 1) is produced from an external clock (CLK). A second signal ( phi 2) is produced from a clock enabling signal (CKE) for controlling an internal clock of a SDRAM. A phase compensated signal ( phi 3) is produced by advancing the phase angle of the signal ( phi 1). A control signal ( phi 4) is produced by a D-type flipflop from the signals ( phi 1 and phi 2). A phase-advanced internal clock ( phi 6) is produced from the signals ( phi 3 and phi 4) through an RS-type flipflop and an OR gate. So, the phase-advanced internal clock ( phi 6) has no hazardous waveform. <IMAGE></p> |
