| 摘要 |
A baseband signal demodulator which ensures, when digital signal processing for data corresponding to one time slot fails to be terminated within a duration of the time slot, a processing clock for the data even in a period exceeding the time slot. In the demodulator, a receive clock reproducer reproduces a receive clock based on a received baseband signal and a phase error data generator generates phase error data indicative of a phase error between the reproduced receive clock and a system clock for control of an entire receiver. Further, a sampling clock generator changes a phase of the system clock based on the phase error data to generate an optimum sampling clock to the baseband signal and a receive data generator generates receive data corresponding to the baseband signal sampled at its optimum positions based on the optimum sampling clock. Thereafter, a data timing adjustor adjusts synchronization of the receive data with the system clock based on the phase error data. Alternatively, a filter coefficient of the filter associated with the phase error between the system clock and the reproduced receive clock to control the phase of the received baseband signal, whereby the baseband signal for a plurality of time slots is synchronized with the single system clock. Thus, demodulation of the baseband signal having different phase errors for the plurality of time slots can be processed by using a single system clock.
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