发明名称 PACKET BUS CONTROLLER
摘要 <p>PURPOSE: To gurantee the order of each packet. CONSTITUTION: A control part 33 controls the packet address information stored in a data packet storage part 31 and an interruption packet storage part 32, packet kind information, the packet transmission waiting state information from a master 2 to the slave 4 and the response waiting state information for the packet from the slave. When a reading control part 34 receives an interruption packet after a data packet is transmitted to the slave 4 based on the contents to be controlled by the control part 33, the control part 34 transmits an interruption packet after the part 34 confirms that the response to the data packet transmitted from the slave 11 is a normal response.</p>
申请公布号 JPH08242252(A) 申请公布日期 1996.09.17
申请号 JP19950045812 申请日期 1995.03.06
申请人 FUJITSU LTD;PFU LTD 发明人 HIKONO ATSUSHI;SAKUKI KENICHI;HOSHI KENJI;SUDO KIYOSHI;KATO TAKANORI
分类号 G06F13/28;G06F13/00;H04L12/40;H04L12/70;H04L29/08;(IPC1-7):H04L12/40;H04L12/56 主分类号 G06F13/28
代理机构 代理人
主权项
地址