发明名称 VITERBI DECODER
摘要 PURPOSE: To reduce the circuit scale of the maximum likelihood judging part of a Viterbi decoder. CONSTITUTION: Comparison and selection circuits 101a, 101b, 101c provided with comparators 103a, 103b, 103c which input plural passmetricsΓi and judge their minimum value, first selectors 104a, 104b, 104c which input the same signals as the plural pass-metrics to be inputted to the comparators and select the passmetrics in conformity with the judgement signals 106a, 106b, 106c of the comparators, and a second selector 105 which selects a discrimination signal to show what passmetric was selected are multistage-connected in the form of a tree. Next, a maximum likelihood judging part which transmits successively the minimum passmetric detected by each comparison and selection circuit to a succeeding stage ad also adds the judgement signal 106 of the comparator to the discrimination signal and makes it the discrimination signal of the succeeding stage is provided.
申请公布号 JPH08242179(A) 申请公布日期 1996.09.17
申请号 JP19950042771 申请日期 1995.03.02
申请人 TOSHIBA CORP 发明人 AIZAWA MASAMI;OKITA SHIGERU
分类号 H04L25/08;H03M13/23;(IPC1-7):H03M13/12 主分类号 H04L25/08
代理机构 代理人
主权项
地址