发明名称 |
Digital signal processor evaluation chip and debug method |
摘要 |
A digital signal processor evaluation chip has a sequencer for fetching and decoding instructions, and a processor core for executing the instructions. When the sequencer attempts to fetch an instruction from a preset break address, a register transfer instruction is supplied in place of the program instruction at that address, then clock input to the sequencer is halted. After the processor core has executed the register transfer instruction, clock input to the processor means is also halted, leaving the data transferred by the register transfer instruction available to be read.
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申请公布号 |
US5557762(A) |
申请公布日期 |
1996.09.17 |
申请号 |
US19940297684 |
申请日期 |
1994.08.29 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
OKUAKI, YASUYUKI;YAMAMOTO, KAZUSHIGE |
分类号 |
G06F11/22;G06F11/36;(IPC1-7):G06F11/25 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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