| 摘要 |
Memory cells are arrange in the row and column directions in the form of a matrix. A transistor as a load is connected to column lines. A sense amplifier is connected to the transistor. In a read check operation, in which the data in the memory cells are erased, and the erased state of each memory cell is checked, all the row lines are set in a non-selected state by a row decoder, and all the column lines are selected by a column decoder. In this state the sum of currents flowing in the memory cells is detected by the sense amplifier. When the current detected by the sense amplifier becomes a predetermined value, a data erase operation is ended.
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