Arbitration device for arbitrating access requests from first and second processors having different first and second clocks

摘要

An arbitration device for shared RAM which arbitrates between first and second requests from first and second processors having respectively different first and second clocks and bus widths which may differ from that of shared RAM. A synchronizer synchronizes the first access request to the second clock so as to obtain clock-synchronized access requests, one of the clock-synchronized access requests is delayed by a fractional part of the second clock so as to yield time-offset access requests, and a hold-off circuit grants access to a first-to-arrive time-offset access request and holds off processing of a second-to arrive time-offset access request until processing of the first access request is complete. A shared RAM interface, responsive to access grant signals from the hold off circuit, gives access to the shared RAM in correspondence to the access grant signal. The shared RAM interface includes a strobe generator for generating upper and lower strobe signals for strobing upper and lower parts of the differently-widthed bus onto shared RAM.