| 摘要 |
PURPOSE: To realize the co-existence of a CPU and a system memory different by supply voltage values and to increase the memory read cycle speed. CONSTITUTION: For the purpose of accessing a system memory 13 operated with 5V by a CPU 11 operated with 3.3V, the data bus of the CPU 11 and the system memory 13 are separated, and a gate array 12 for level shift which converts the voltage level of a data signal in two directions is inserted between them. The gate array 12 for level shift is provided with a latch circuit, and the read cycle of the system memory 13 and the bus cycle of the CPU 11 are asynchronously executed. Thus, the number of waits inserted to the bus cycle of the CPU 11 is reduced at the time of burst read. |
