发明名称 |
METHOD OF FABRICATION OF SEMICONDUCTOR DEVICE |
摘要 |
PURPOSE: To provide a method of fabrication of a semiconductor device capable of easily achieving flattening on an insulating layer such as a BPSG layer and an SOG layer and of applying wiring and the like with high reliability and redundance in a later process. CONSTITUTION: There is provided a method of fabrication of a semiconductor device such as a dynamic RAM wherein upon flattening a layer (e.g. a BPSG layer 66) including a step (e.g. global step 62) formed with an upper part (e.g. a part on a memory cell array part MA) and a lower part (e.g. a part on a peripheral circuit part PC) a resist layer 70 is formed into a predetermined pattern such that an end part is located on a slope 62A forming the step part 62 after preannealing. A higher layer 66 than the resist layer is uniformly removed by etching by a predetermined thickness using the resist layer as a mask, and thereafter a protruded part (e.g. a protrusion 66A produced after the etching) existent on a lower side than the resist layer 70 is eliminated with a reflow processing in the state where the resist layer T670 is removed. |
申请公布号 |
JPH08236724(A) |
申请公布日期 |
1996.09.13 |
申请号 |
JP19950310141 |
申请日期 |
1995.11.02 |
申请人 |
TEXAS INSTR JAPAN LTD |
发明人 |
ASHIGAKI SHIGEO;HAMAMOTO KAZUHIRO |
分类号 |
H01L21/31;H01L21/302;H01L21/3065;H01L21/3205;H01L21/768;H01L21/8242;H01L27/108 |
主分类号 |
H01L21/31 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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