| 摘要 |
PROBLEM TO BE SOLVED: To prevent the risk of a short circuit due to increase in the degree of integration, by previously forming a bit line and then forming a contact hole through the inside of the bit line, so as to secure an alignment margin between the bit line, a word line and a storage node contact. SOLUTION: A gate electrode 47 and a bit line pattern 34 are formed on MOS structure, and each insulated layer is etched to form a polycrystalline silicon spacer 39. After a fifth insulated layer 40 is deposited and flattened on it, a contact hole connecting the bit line 34 and a drain region 46 is formed. Next, a fourth polycrystalline silicon layer 42 is vapor-deposited to fill the hole. Through the use of a third mask pattern 43, polycrystalline silicon at a surrounding part is etched to form bit line contact. Next, each of insulated layers 34 to 37, 40 and 44 at a lower part is successively etched through the use of a fourth mask pattern 45 to form a storage node contact hole eexposing a source region. |
