CONDITIONAL LATCHING MECHANISM AND PIPELINED MICROPROCESSOR EMPLOYING THE SAME

摘要

A conditional latch circuit is provided wherein a first transmission gate is electrically coupled in series with a second transmission gate between an input node and an output node. The latch circuit is controlled by a conditional clock signal wherein a delay element is employed to cause both transmission gates to be simultaneously enabled upon an edge of the conditional clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input node is electrically coupled to the output node. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input node is decoupled from the output line by disabling the first transmission gate. An edge of the conditional clock signal which causes a new input value to be latched within the latch circuit is driven by a logic gate which receives a clock signal at a first input, a condition signal at a second input, and an inhibit signal at a third input. The inhibit signal is provided from an inhibit signal generator and is provided to prevent the false-firing of the latch if the condition signal is asserted while the clock signal is active.