PARALLEL ACCESS MICRO-TLB TO SPEED UP ADDRESS TRANSLATION

摘要

A memory management unit (124) (MMU) includes a translation lookaside buffer (108) capable of simultaneously servicing three requests supplied to the MMU by an instruction cache (102) and two data caches (103, 104), respectively. Also, an arbiter (113) selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.