| 摘要 |
<p>The shift register includes a source of several phase shifted clock signals and several cascaded stages. Each stage is provided with two transistors of a push-pull amplifier, an input section, and a switching transistor. The first push-pull transistor responds to a first clock signal to generate an output pulse at a given stage output. The input section is responsive to an output pulse developed at an output of a second stage when a clock signal phase shifted w.r.t the first clock signal occurs. The input section then generates a control signal at a control electrode of the first transistor to generate the output pulse of the given stage when an active level of the first clock signal occurs. The second push-pull transistor is coupled to the given stage output for clamping the output to an inactive level. The switching transistor responds to an output pulse of a downstream stage to apply a control signal to the second transistor.</p> |
