发明名称 Method and apparatus for calculating a divider in a digital phase lock loop
摘要 <p>The method involves comparing (12) a reference oscillation (26) with a feedback oscillation (28), at a triggering event, to produce an error signal (30,32). The error signal is compared with a coarse threshold (36) and, if it compares unfavourably, a coarse divisor adjustment (40,18) is provided to a feedback divider (20). If the error signal compares favourably with the coarse threshold, it is compared with a fine threshold (38). If it compares unfavourably with the fine threshold, a fine divisor adjustment (42,18) is provided to the feedback divider.</p>
申请公布号 EP0731564(A2) 申请公布日期 1996.09.11
申请号 EP19960103054 申请日期 1996.02.29
申请人 MOTOROLA, INC. 发明人 GIRARDEAU, JAMES W., JR.
分类号 H03L7/06;H03L7/089;H03L7/095;H03L7/099;H03L7/187;H03L7/197;H03L7/199;(IPC1-7):H03L7/099 主分类号 H03L7/06
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