发明名称 |
Charge domain bit-serial multiplying digital-analog converter |
摘要 |
A single chip adaptive filtering system including an FIR filter and circuitry for calculating updated weighting coefficients for use in associated multiplying digital-to-analog converters. The adaptive FIR filter performs the convolution of a delayed and sampled input sequence to produce a filter output. Thereafter, an error term is determined by calculating the difference between the filter output and a reference signal which corresponds to a predetermined anticipated output of the filter. The error term is then applied to a least mean square (LMS) estimation algorithm for computing updated weighting coefficients to be used by the adaptive FIR filter.
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申请公布号 |
US5555200(A) |
申请公布日期 |
1996.09.10 |
申请号 |
US19950457827 |
申请日期 |
1995.06.01 |
申请人 |
MASSACHUSETTS INSTITUTE OF TECHNOLOGY |
发明人 |
CHIANG, ALICE M. |
分类号 |
H03H21/00;(IPC1-7):G06J1/00 |
主分类号 |
H03H21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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