发明名称 |
Dynamic semiconductor memory device |
摘要 |
A NAND type DRAM includes a plurality of NAND cells disposed on intersections between a plurality of word lines and a plurality of bit lines, a plurality of sense amplifiers each for sensing and amplifying the potential difference between two bit lines of each bit line pair among the plurality of bit lines, first switching sections for sequentially selecting those bit lines of the plurality of bit lines which are connected to the sense amplifier in a paired form, and second switching sections for sequentially changing the combination of a bit line pair constructed by bit lines selected by the first switching sections, and two bit lines disposed adjacent to and on both sides of a bit line to which the NAND cell is electrically connected are connected to the sense amplifier in a paired form by the first and second switching sections.
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申请公布号 |
US5555203(A) |
申请公布日期 |
1996.09.10 |
申请号 |
US19940358582 |
申请日期 |
1994.12.13 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIRATAKE, SHINICHIRO;OHUCHI, KAZUNORI;TAKASHIMA, DAISABURO |
分类号 |
G11C11/408;G11C11/4096;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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