发明名称 |
Activity masking with mask context of SIMD processors |
摘要 |
Disclosed is a masking technique for a SIMD processor (10) which is capable of masking a plurality of individual machine operations within a single instruction incorporating a plurality of operations. To accomplish this each different machine operation within the instruction includes a number of masking bits which address a specific location in a mask register (60). The mask register (60) includes a mask bit bank (62). The mask location selected within the mask register (60) is bit-wise ANDed with a mask context bit (66) in order to establish whether the processing element will be enabled or disabled for a particular conditional sub-routine which is called. One of the bit locations in the mask bit bank (60) is a hard-wired unconditional bit which overrides the mask context bit (66) in order to enable the processing elements in special situations. In addition, a scalar mask bit is provided to facilitate scalar processing. By this operation, instructional parallelism can be incorporated in order to increase through-put of the processor. |
申请公布号 |
US5555428(A) |
申请公布日期 |
1996.09.10 |
申请号 |
US19950402406 |
申请日期 |
1995.03.10 |
申请人 |
HUGHES AIRCRAFT COMPANY |
发明人 |
RADIGAN, JAMES J.;SCHWARTZ, DAVID A. |
分类号 |
G06F15/16;G06F9/38;G06F15/80;(IPC1-7):G06F15/80 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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