Modified BP-TEOS tungsten-plug contact process

摘要

An improved method for the fabrication of an ohmic, low resistance contact to heavily doped silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for surface planarizatiion by depositing first a layer of silicon oxide followed by a layer of borophosphosilicate glass onto a silicon wafer containing integrated circuit devices. After the glass is thermally flowed to planarize its surface, it is etched back to a suitable thickness and a second layer of silicon oxide is deposited over the now-planar surface. Contact holes are patterned in the composite silicon oxide-glass-silicon oxide structure and the exposed silicon device contacts are ion-implanted. The implant is then activated by rapid-thermal-annealing. The presence of the second silicon oxide layer prevents the upper corners of the contact openings from flowing and encroaching into the opening as would occur in its absence. Not only does this provide for void-free filling of the contact openings by the tungsten contact deposition but it also permits the use of higher temperatures for the implant anneal.