| 摘要 |
A barrel shifter for shifting a plurality of bits in a single clock cycle has a bypass circuit through which unshifted results from an arithmetic logic unit (ALU) are bypassed around a shift circuit and provided directly to an output of the barrel shifter. An isolation circuit having tristate inverters isolates the shift circuit of the barrel shifter from the ALU results when the results are not to be shifted so that internal signal nodes of the shift circuit with high capacitance will not be switched. When the results are to be shifted, the tristate inverters of the isolation circuit are enabled to pass the results to the shift circuit where they are shifted and then provided to the barrel shifter output. By providing the results to the shift circuit only when a shift is to be performed, and otherwise isolating the shift circuit, power consumption is reduced.
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