发明名称 Multipurpose error correction calculation circuit
摘要 A bit-oriented error correction calculation circuit performs numerous mathematical operations including bit-oriented convolutions, inversions, multiplications, additions, and bi-directional basis conversions. The circuit includes three banks of registers (400,401,402) connected as a convolution circuit to produce a sequence of inner products with respect to the first bank of registers (400) and the second bank of registers (401). Each of the banks of registers (400,401) has a bank loading switch (440,441,442) connected to a serial input terminal thereof for loading a selected one of a plurality of serial multibit values into the banks, including selective gating of feedback signals from respective feedback circuits (450,452) in registers (400,402) and (inter alia) constant values. The values of the feedback multipliers are selectively changeable in accordance with a field length of the value involved in error correction of data. Further included are a summation circuit (320); a comparison circuit (360); and a bi-directional conversion unit for converting an m-bit input value from an input basis representation to an output basis representation.
申请公布号 US5555516(A) 申请公布日期 1996.09.10
申请号 US19940306918 申请日期 1994.09.16
申请人 CIRRUS LOGIC, INC. 发明人 ZOOK, CHRISTOPHER P.
分类号 G06F7/52;G06F7/00;G06F7/535;G06F7/72;G06F7/76;G06F11/10;G06F17/10;G11B20/10;G11B20/18;H03M13/00;H03M13/15;H03M13/35;H03M13/37;(IPC1-7):G06F7/00;G06F15/00 主分类号 G06F7/52
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