发明名称 |
CLOCK SYNCHRONIZATION METHOD OF DISTRIBUTED MULTIPLE PROCESSING SYSTEM WITH LOOSELY COUPLED STRUCTURE |
摘要 |
establishing a system clock control block 21 in a system clock operating processor; performing an environment construction for clock synchronization by the first operating the system clock control block 21 in the processor to establish a local clock control block 22 in SMP 7 originated in FEP 2, 3 and BEP 4, 5 as a transaction processor; driving a local clock control block 22; generating a system standard clock in a system clock control block to re-control a local clock in order to accord the system standard clock by operating the local clock control block 22 in the processor as a standard clock to receive a change- finished message from the local clock control block 22 in all processors to output it into a clock synchronization result output device.
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申请公布号 |
KR960011967(B1) |
申请公布日期 |
1996.09.06 |
申请号 |
KR19930026292 |
申请日期 |
1993.12.02 |
申请人 |
KOREA ELECTRONICS & TELECOMMUNICATION RESEARCH INSTITUTE;KOREA TELECOM CORP. |
发明人 |
PARK, KYUNG - JOON;CHO, PYUNG - DONG |
分类号 |
H04L12/427;(IPC1-7):H04L12/427 |
主分类号 |
H04L12/427 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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