| 摘要 |
PURPOSE:To perform characteristic testing readily and highly efficiently, by performing the characteristic testing of IC chip regions under the wafer state wherein a plurality of aligned IC chip regions are provided. CONSTITUTION:Each part, which is shown by a square shape, is an IC chip region 1. Dicing regions 2, which are divided in to the individual chips by dicing, are provided between the IC chip regions, which are aligned in the lateral direction. A pair of power source lines 3 and 4, which is common to each IC chip region, is provided at the upper and lower rows. A pair of common power source terminals 5 and 6, which is common to each row, is provided at the peripheral part of a semiconductor wafer 7. The power source lines 3 on the rows are commonly connected to the power source terminal 5. The other power source lines 4 on the rows are commonly connected to the power source terminals 6. Since the characteristic test of the IC chip regions is performed under the wafer state having a plurality of aligned IC chip regions, the characteristic testing can be performed readily and highly efficiently.
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