Semiconductor package device and method for calculating a parasitic capacitance generated by a molding material

摘要

High speed integrated circuits are designed and fabricated by taking into account the capacitive loading on the integrated circuit by the integrated circuit potting material. Line drivers may be sized to drive conductive lines as capacitively loaded by the potting material. Repeaters may be provided along long lines, to drive the lines as capacitively loaded by the potting material. Intelligent drivers may sense the load due to the potting material and drive the lines as capacitively loaded by the potting material. The thickness of the passivating layer on the outer conductive lines may also be increased so as to prevent the potting material from extending between the conductive lines. High speed potted integrated circuits may thereby be provided.