| 摘要 |
<p>PURPOSE: To reduce fabrication cost of EEPROM while controlling fluctuation of threshold value of a memory cell transistor. CONSTITUTION: An N-type well and an N-type ground wiring layer are diffused and formed into a P-type substrate, the word lines using P-type polysilicon are formed in the N-type well, the drain region and source region of memory cell transistor are formed by ion implantation of arsenic into the P-type substrate adjacent to the N-type well, and floating gates are continuously formed keeping the predetermined interval on the channel region and word line region provided between the drain region and source region. The P-type polysilicon provided opposed to the floating gates works as a control gate of the memory cell transistor. When a pulse which alternately repeats +3V and -10V is applied to the word lines, the threshold value of the memory cell transistor is converged to the value corresponding to +3V of this pulse.</p> |
