发明名称 MANUFACTURE OF DRAM UNIT CELL AND ITS ARRAY OR DRAM UNIT IN SUBSTRATE
摘要 PROBLEM TO BE SOLVED: To provide a DRAM unit cell whose occupation area in a substrate is made minimum. SOLUTION: A trench capacitor 22, an operation word line 36 and a planar- type FET 26 are provided. The trench capacitor has a signal electrode 24 and a bit line 48. The operation word line 36 is made to overlap the trench capacitor. The conducting route of the planar-type FET is connected between the signal electrode 24 and bit line 48 of the trench capacitor, and the gate electrode of the planar-type FET is composed of the operation word line 36.
申请公布号 JPH08227981(A) 申请公布日期 1996.09.03
申请号 JP19950297075 申请日期 1995.11.15
申请人 SIEMENS AG 发明人 YOHAN ARUSUMAIAA;MARUTEIN GARU
分类号 H01L21/8242;H01L27/108 主分类号 H01L21/8242
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