| 摘要 |
PURPOSE: To reduce the circuit scale of the serial/parallel converting circuit for inputting two kinds of serial data which are different just for a half clock cycle. CONSTITUTION: A flip-flop 8 is provided to delay a serial data signal SI, which contains two kinds of serial data made different just for the half clock cycle, just for the half clock cycle and the serial data signal SI and a delayed perial data signal SI are switched by a switching circuit 9 and transmitted to a shift register 1. At the time of serial data advanced just for the half clock cycle, the serial data signal SI' is transmitted to the shift register 1 but at the time of serial data delayed just for the half clock cycle, on the other hand, the serial data signal SI is transmitted to the shift register 1 as well. A clock signal CLK1 of the shift register 1 is limited to one kind and a control signal C1 of a storage register 2 is limited to one kind. |
