BURN-IN TEST CIRCUIT OF SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To obtain a burn-in test circuit capable of performing a fail screening under both states of a wafer and a package and applying a stress voltage at one time to a plurality of word lines. SOLUTION: A burn-in enable circuit 15 generates a burn-in enable signal BE when a timing of respective external signals such as a bar RAS, a bar CAS, a bar W is set. In response to this signal BE, a low address decoder 12 makes a word line floating, and a word line stress input circuit 14 applies a stress voltage from a Vcc terminal to a word line. Further, when the respective external signals are given at another timing, a burn-in completion signal FBE is generated, and in response to this, a burn-in suppression circuit 16 continuously generates a burn-in suppression signal MSTR, thereby suppressing operations of the burn-in enable circuit 15.