| 摘要 |
<p>PURPOSE: To secure the set-up time of an input signal and to accelerate an access to a synchronous DRAM by changing the frequency of a signal to be supplied to the DRAM. CONSTITUTION: At the time of receiving an access request from a CPU, a CPU I/F unit turns a RAMREQ from CLKO to a low (L) level and requests bus using right to an arbiter. The arbiter secures the access request receivable state of an SDRM control unit, judges the absence of a request with high priority, recognizes the acceptance of the RAM access by turning a 1st RAMCK to an 'L' level and requests the reduction of the oscillation frequency of a clock from a CLK 2 by turning a LOW signal to the 'L' level. Simultaneously a low address is driven to an RA to be an address bus for the SDRAM and the low address is inputted to an RAS by turning a CS to the 'L' level. A CLK 4 requests to turn the LOW to a high(H) level and return the clock frequency to the original band.</p> |
