Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock

摘要

An apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock that are substantially synchronous. The low-frequency clock is frequency divided-by-two generate a Lfdiv2 signal. The Lfdiv2 signal is synchronously delayed by one phase of the high-frequency clock to generate a dLFdiv2 signal. The LFdiv2 and dLFdiv2 signals are compared an XOR gate to generate a PH1 signal. A rising-edge of the PH1 signal indicates that a rising-edge of the high-frequency clock corresponds to a rising-edge of the low-frequency clock. This phase information allows enhanced communication between state machines or buses that are operating at different frequencies.