High performance energy efficient push pull D flip flop circuits

摘要

An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase having an input connected to the output of the inverter and an output connected to the output of the slave latch. This push-pull circuit speeds the C-to-Q delay time of the circuit because there is only one gate delay to output using this circuit. The master and slave latches may employ P-type MOSFETs in the feedback path. The master latch may employ a double pass transistor logic input. The push-pull circuit may employ a tri-state invertor in place of the inverter and transmission gate.