| 摘要 |
PURPOSE: To provide the CMOS integrated circuit which can suppress a through current without disturbing high integration. CONSTITUTION: The gates of a PMOS transistor QP11 and an NMOS transistor QN11 at an inverter 11 are commonly connected to an input terminal Na and data are transferred from a latch circuit 13 to here. An auxiliary PMOS transistor QP12 is interposed on the PMOS side of the inverter 11 and an auxiliary NMOS transistor QN12 is interposed on the NMOS side. Another inverter 12 is similarly constituted as well. A timing control circuit 15 is provided commonly for the inverters 11 and 12 and generates a first control clockϕ1 for controlling latch circuits 13 and 14 by delaying a reference clockϕ0. Then, a second control clockϕ2 is generated to keep the auxiliary PMOS transistor QP12, QP22, auxiliary NMOS transistor QN12 and QN22 turned off for the prescribed time of the output transition of the inverters 11 and 12.
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