SYNCHRONIZING SIGNAL DETECTION CIRCUIT

摘要

PURPOSE: To prevent mis-detection of a frame synchronizing signal and reduction in the detection frequency. CONSTITUTION: Frame synchronizing signals have non-correlation between two lines and between 4 clocks. A correlation detection means 2 detects respectively non-correlation between two lines and a correlation detection means 3 detects non-correlation 4 clocks. Simultaneously the non-correlation is detected, an AND gate 4 provides an output of an H signal. A control means 5 counts up a counter 6 when the output signal is logical H and counts down the counter 6 when the output signal is logical L and is reset when logical L is consecutive for a prescribed period. When the count of the counter 6 exceeds a threshold level (n), a comparator 7 provides an output of a synchronization detection signal. A counter 11 is reset when the counter 6 is reset simultaneously to count clock signals from an input terminal 10 and a comparator 12 generates a timing signal when the count is within a lower limit m1 and an upper limit m2. When the synchronization detection signal and the timing signal are generated simultaneously, a synchronization discrimination means 9 discriminates a frame synchronizing signal.