DIGITAL DATA TRANSMITTER, RECEIVER AND DIGITAL DATA COMMUNICATION SYSTEM

摘要

PURPOSE: To improve a reception threshold level and to reduce a multi-path fault by providing an output of preamble data comprising specific code data synchronously with a timing pulse. CONSTITUTION: A clock frequency divider 202 frequency-divides a inputted reference clock signal and outputs a timing pulse specifying a bit timing of transmission data. A timing pulse outputted from the clock frequency divider 202 is also fed to a preamble data generating circuit 204, which outputs a PN code in a timing specified by the timing pulse. The correlation is detected with high accuracy by adopting the PN code having a steep autocorrelation characteristic as the preamble data and each bit in the received data signal is accurately separated. Thus, high data decoding performance is obtained even when noise due to deteriorated S/N or multi-path is intruded in the received bits.