| 摘要 |
PURPOSE: To make a flicker display for a long packet by using a comparatively simple circuit configuration and to display even a short packet at a flickering speed to be recognized accurately by eyes. CONSTITUTION: A 2nd latch means FF2 detects a carrier by using an output of a 1st latch means FF1 to latch a packet transmission or reception information signal A by using a clock B whose speed is sufficiently high as a clock signal, a 4th latch means FF4 latches an output of a 3rd latch means FF3 to latch its carrier detection output with a clock signal C whose frequency results in a visible flickering by using the clock signal C, the 1st to 4th latch means FF1-FF4 are reset by an output of a 5th latch means FF5 latching an output of the 4th latch means FF4 by using the clock signal B, and an exclusive OR between an output of the 3rd latch means FF3 and a packet transmission or reception information signal A is used for a display output signal S. |
