发明名称 PARITY GENERATION AND CHECK CIRCUIT
摘要 <p>PURPOSE: To confirm whether a memory for parity and a parity generation and check circuit operate normally or not in the parity generation and check circuit. CONSTITUTION: In the parity generation and check circuit which generates a parity by an inspection circuit 302, and stores it in the memory 204 for parity at the time of writing data in the memory 203 for data from a microcomputer, and besides, executes the operation check of the memory 203 for data by executing the parity check of the read out data and the stored data at the time of reading the data out of the memory 203 for data, only one bit among the read out data is read out of the memory 204 for parity instead of the memory 203 for data by the microcomputer.</p>
申请公布号 JPH08221282(A) 申请公布日期 1996.08.30
申请号 JP19950024221 申请日期 1995.02.13
申请人 HITACHI CABLE LTD 发明人 AOKI TERUAKI
分类号 G06F11/08;G06F12/16;(IPC1-7):G06F11/08 主分类号 G06F11/08
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