发明名称 |
Cache testing using a modified snoop cycle command |
摘要 |
The cache controller of a second level cache in an Intel Pentium processor based computer system contains test circuitry that allows reading and writing directly into all tag RAM databit locations. This circuitry responds to a modified External Address Strobe (EADS#) command to invoke the tag test cycle. The EADS# command is normally used in a SNOOP read cycle by the system. In a SNOOP cycle, the main memory controller invokes the EADS# command to request the first level (L1) and second level (L2) caches for modified information stored in those caches. In the tag test cycle the EADS# command line is held down twice as long as it would in a normal SNOOP read Cycle. Because of its added length, the SNOOP cycle circuits in the L2 cache ignore the command on the EADS# command line. However, the tag RAM test circuitry in the L2 cache recognizes the extended EADS# strobe providing a path to access all bit locations in a tag RAM for both read and write cycles to test the tag RAM or to load those bit positions to selected states in testing other portions of the cache. <IMAGE> |
申请公布号 |
EP0729100(A1) |
申请公布日期 |
1996.08.28 |
申请号 |
EP19960101169 |
申请日期 |
1996.01.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHIN, HENRY;TOTOLOS, GEORGE, JR. |
分类号 |
G06F12/16;G06F12/08;G11C29/24;G11C29/46 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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