| 发明名称 |
Voltage-controlled delay unit for delay-locked loop devices |
| 摘要 |
<p>The delay unit (UR) comprises one or more stages (R1...Rn) each including a chain of inverters (IN1...IN4). A capacitive load is applied to the output node of each inverter. That load is made to vary by a voltage control signal and is made up by the gate capacitance of a P transistor (Tp1...Tp4). <IMAGE></p> |
| 申请公布号 |
EP0729231(A2) |
申请公布日期 |
1996.08.28 |
| 申请号 |
EP19960102656 |
申请日期 |
1996.02.22 |
| 申请人 |
CSELT CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S.P.A. |
发明人 |
TORIELLI, ALESSANDRO |
| 分类号 |
H03H11/26;H03K5/13;H03L7/081;H03L7/089;H04L7/033;(IPC1-7):H03K5/13 |
主分类号 |
H03H11/26 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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