| 摘要 |
<p>PURPOSE:To shorten the design time and to expand the application range by adopting the constitution provided with a frequency division function for a PLL circuit and a pulse width modulation function for voltage synthesizer with a counter circuit, a data storage circuit and a data selection circuit. CONSTITUTION:A selective signal SS is used to select 1st and 2nd clock pulses CK1, CK2, a data stored in a data storage circuit 3 and a function of a data selection circuit 4. When the selective signal SS is at a high level, the signal is used to apply frequency division to the 1st clock pulse CK1 and when the selective signal SS is at a low level, the signal is used to generate a PWM signal from the 2nd clock pulse CK2 as a PLL. Thus, the circuit is applied for a device, etc., having a PLL circuit, a voltage synthesizer and using them switchingly and the circuit of this design is applicable to lots of kinds of the devices.</p> |
