| 摘要 |
<p>An image signal processing apparatus is provided comprising an image sensor (1) for outputting image data, a sample hold circuit (2) for holding the image data output. The sample hold circuit outputs an analog signal to an AD converter (3) for converting the analog signal to a digital signal. A system clock generator (6a) generates a first clock signal ( phi 1), while a timing generator (4) controls the hold timing of the sample hold circuit (2) according to the first clock ( phi 1). A second system clock generator (6b) generates a second system clock signal ( phi 2) having a different phase from the phase of the first clock signal ( phi 1). An AD conversion clock generator (5) controls the conversion timing of AD converter (3) according to the second clock ( phi 2). Since two different clocks are used, the hold timing does not overlap with a conversion timing. Therefore, the reading of the image data becomes stable and misreading can be reduced, where the quality of an image is improved. <IMAGE></p> |
