| 摘要 |
PURPOSE:To decrease timing deviation between a modulation signal and a clock signal by comparing the phase of the modulation signal and that of the clock signal and using a voltage controlled oscillator (VCO) so as to control the frequency of the clock signal. CONSTITUTION:The VCO 2 generates a clock signal, which is supplied to a phase comparator 3 and a changeover switch 6. Then the phase comparator 3 compares the phase of the modulation signal and that of the clock signal, and a frequency control signal having an error voltage in response to the phase is supplied to the VCO 2 to control the frequency of the clock signal. Then a reference frequency signal generator 5 generates a reference frequency signal of a single frequency, which is fed to a changeover switch 6. The changeover switch 6 is subject to switching control by a control signal (b) from a control signal generating circuit 11 and the clock signal when the control signal (b) is at L level is selected. Thus, the timing between the modulation signal and the clock signal is not deviated from the optimum state. |
