发明名称 Schematic generator and schematic generating method
摘要 Disclosed is here units or processing steps respectively for detecting loops in a logic circuit to determine logic levels associated with first coordinates of respective elements such that a location where the overlapping of the loops develop the maximum value is assigned as a feedback routing, for determining positional relationships between elements at the reference level to relieve congestion of routings in the vicinity of the reference level, for sequentially achieving the maximum matching on a bipartite graph constituted with connective relationships of the elements for each level beginning from the reference level to determine positional relationships related to second coordinates so as to assign elements associated with each other to the same position, and for defining virtual routing length to achieve routing in accordance with a result of sorting by use of the virtual routing lengths.
申请公布号 US5550714(A) 申请公布日期 1996.08.27
申请号 US19890403452 申请日期 1989.09.06
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD. 发明人 NISHIYAMA, TAMOTSU
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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