发明名称 |
Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop |
摘要 |
A phase-locked loop wherein the output signal is effectively sampled at an increased rate from conventional phase-locked loops, allowing for a greater increase in the ratio of the output frequency to the input frequency while reducing the possibility of jitter or failure to lock. Multiple differently phased reference signals and correspondingly phased feedback signals are produced. The comparison of the feedback signals and the reference signals produce multiple error signals which are combined to adjust the oscillation frequency of the voltage-controlled oscillator.
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申请公布号 |
US5550515(A) |
申请公布日期 |
1996.08.27 |
申请号 |
US19950378798 |
申请日期 |
1995.01.27 |
申请人 |
OPTI, INC. |
发明人 |
LIANG, JUI;CO, RAMON;GUI, ANN |
分类号 |
H03L7/07;H03L7/087;H03L7/089;H03L7/099;H03L7/191;(IPC1-7):H03L7/07;H03L7/18 |
主分类号 |
H03L7/07 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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