| 摘要 |
A bi-modal trigger circuit for ESD protection in an IC is arranged to use the energy of the ESD event itself to trigger an SCR when VDD is absent and energy from VDD when VDD is present. This is accomplished by top and bottom inverters in series, and a trigger FET whose conduction triggers an SCR, and whose gate is driven by the voltage across the bottom inverter. The trigger threshold of the bi-modal trigger circuit may be raised above VDD when VDD is absent by the inclusion of a constant voltage drop inserted between the series connected top and bottom inverters that comprise the bi-modal trigger. This provides an offset voltage that must be overcome before a trigger FET can turn on and fire an SCR that does the actual ESD protection. The constant voltage drop may be produced by a series string of diode connected FET's. The threshold may also be increased by including a latch-connected feedback FET that shunts the gate of the trigger FET, thereby retarding the turn-on of the trigger FET until saturation in the feedback FET trips the latch. These two techniques can be used separately or in combination. When used in combination the number of diode connected FET's may be reduced to provide a constant voltage drop that is substantially less than the desired increase in the trigger voltage for the bi-modal trigger circuit.
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